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Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

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6 Author(s)
Ya-Ting Shyu ; Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan ; Jai-Ming Lin ; Chun-Po Huang ; Cheng-Wu Lin
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Power has become a burning issue in modern VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Given a design, we can reduce its power consumption by replacing some flip-flops with fewer multi-bit flip-flops. However, this procedure may affect the performance of the original circuit. Hence, the flip-flop replacement without timing and placement capacity constraints violation becomes a quite complex problem. To deal with the difficulty efficiently, we have proposed several techniques. First, we perform a co-ordinate transformation to identify those flip-flops that can be merged and their legal regions. Besides, we show how to build a combination table to enumerate possible combinations of flip-flops provided by a library. Finally, we use a hierarchical way to merge flip-flops. Besides power reduction, the objective of minimizing the total wirelength is also considered. The time complexity of our algorithm is \Theta ({\rm n}^{1.12}) less than the empirical complexity of \Theta ({\rm n}^{2}) . According to the experimental results, our algorithm significantly reduces clock power by 20–30% and the running time is very short. In the largest test case, which contains 1 700 000 flip-flops, our algorithm only takes about 5 min to replace flip-flops and the power reduction can achieve 21%.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:21 ,  Issue: 4 )