By Topic

Efficient Wafer-Level Edge-Tracing Technique for 3-D Interconnection of Stacked Die

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Sun-Rak Kim ; Dept. of Mech. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Lee, P. ; Jae-Hak Lee ; Jun-Yeob Song
more authors

An efficient edge-tracing technique at the wafer-level is proposed and implemented in this paper. The proposed method can be applied to the fabrication of a stacked chip. Experiments were conducted by stacking four test chips each 100-μm-thick, and the configuration of the pad is based on a memory chip from an electronics company. The chips for stacking were fabricated by half-dicing the wafer and curing the adhesives in a trench. When the four chips were built up and metallized, the stacked chip was 430-μm high, which is comparable to that of a through-silicon via. The daisy chain resistance of the interconnection was measured to be 5 Ω, and further improvement is possible with modification. The interconnection quality of the stacked chip was examined through 3-D images obtained via computed tomography and X-ray imageries. The images proved the successful creation of the interconnections. The mechanical integrity of the stacked package meets the 85°C/85% relative humidity test, and the thermal stress analysis is implemented to investigate the reliability issues at the edge of the chip, and it is concluded that there are no critical reliability problems.

Published in:

Components, Packaging and Manufacturing Technology, IEEE Transactions on  (Volume:2 ,  Issue: 6 )