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Multiprocessor on chip (MPSoC) with network on chip (NoC) are strongly emerging as prime candidates for complex embedded applications. In a general ESL design methodology and for significant size designs the use of prototyping and emulation through FPGA is necessary for intensive validation and test as well as careful design space exploration. Moving a design from FPGA to ASIC questions the gains and benefits which can be achieved both at an architectural level but also at the parallel programming level. In his paper we analyze the migration of an implemented, validated and tested single FPGA chip multiprocessor with network on chip towards 65nm and 45nm ASIC technologies. Our results show that although we can naturally expect an area gain, the working frequency is not significantly augmented in 45nm. This suggests that performance improvement can not be achieved by technology alone and area advantage should be exploited by selecting network on chip components with more aggressive features. This in turn affects parallel programming.