By Topic

An FPGA-based implementation of HW/SW architecture for CFAR radar target detector

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Djemal, R. ; Electr. Eng. Dept., King Saud Univ., Riyadh, Saudi Arabia ; Belwafi, K. ; Kaaniche, W. ; Alshebeili, S.A.

This paper presents an efficient HW/SW Codesign FPGA-based architecture of B-ACOSD CFAR target detector in log normal distribution for radar system. All CFAR system modules are analyzed in order to identify the critical ones to be optimized so that the detection process will be conducted in realtime. To compel the design optimization of CFAR Architecture, we have considered the custom instruction approach offered by Altera environment. Furthermore HW/SW architecture of the CFAR detector is carried out where the NIOS II execute the software part and communicate via the Avalon switch fabric with the hardware modules represented by the custom logic components, on-chip memories, UART and JTAG interfaces. The proposed system-on-chip is validated and tested using the Stratix IV EP4SGX230KF4C2 of Altera operating at 250MHz. Using the HW/SW approach for our embedded target detection system, we improved the performance of the architecture compared to the pure software one with a total delay of 0.45 μs.

Published in:

Microelectronics (ICM), 2011 International Conference on

Date of Conference:

19-22 Dec. 2011