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Tri-state inverter based DCO are emerging as an attractive circuit for the implementation of fully digital PLL. In this paper, we first introduce an analytical expression of the tuned period as a function of design and technology parameters. Then, we propose a sizing methodology for the CMOS implementation of a tri-state inverter based DCO. Finally, we applied this methodology to the design of such a DCO. We achieved an average error of 5.4% for our analytical expression compared to simulation results. In conclusion, we showed that our analytical expression and sizing methodology are directly applicable to the design of tri-state inverter based DCO.