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This study presents a 6-bit 2.7 GS/s low-power digital-to-analogue converter (DAC) for ultra-wideband transceivers. A 2(thermometer) 4(binary) segmented architecture is chosen to reach a compromise between the current source cell s area and the operating speed of the thermometer decoder. In addition, the proposed pseudo-thermometer structure improves the DAC s dynamic performance. The bipolar current source cell and latch clock delay technique are employed to reduce the power consumption in the analogue and digital parts, respectively. Moreover, the compact de-glitch latch presented in this study simplifies the conventional latch design and layout. This DAC was implemented in a standard 0.13 m 1P8M complementary metal-oxide semiconductor technology with the active area of 0.0585 mm2. The measured differential non-linearity and integral non-linearity are less than 0.09 and 0.11 least significant bit, respectively. The measured spurious-free dynamic range is more than 36 dB over the Nyquist frequency at the sampling frequency of 2.7 GHz. The DAC consumes 5.4 mW with a near-Nyquist sinusoidal output at 2.7 GS/s, resulting in a better figure of merit of 31 fJ/conversion-step than other published arts.
Date of Publication: March 2012