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Design methodology for on-chip bus architectures using system-on-chip network protocol

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1 Author(s)
J. Lee ; Department of Electronic Engineering, Korea National University of Transportation, Korea

As the number of IP cores that can be integrated into a single chip has increased significantly in recent years, various types of multi-layered bus architectures are now being used. However, a reckless use of bus layers may lead to an excessive number of wires and low-resource utilisation. To reduce such waste, researches have studied automated on-chip bus design methods for optimal architecture synthesis. This study expands the existing studies in two aspects. First, it considers all possible topologies and redefines the existing exploration problem, whereas the existing studies assume only a few types of topologies. Second, the study includes an exploration process based on a new on-chip bus protocol, system-on-chip network protocol (SNP), as well as processes based on existing protocols to solve the redefined problem. After the time complexity is investigated, it is found that the problem is NP-hard. Accordingly, this study proposes fast search algorithms that can be applied to each of the exploration steps. The proposed algorithms are implemented as a software program of exploration. The overall reduction ratio of the time complexity reaches about three millionths, with a maximal 16% increase in communication time (CT). Considering todays design life cycle, this seems to be a good trade-off.

Published in:

IET Circuits, Devices & Systems  (Volume:6 ,  Issue: 2 )