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13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO

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8 Author(s)
Hirairi, K. ; Semicond. Technol. Acad. Res. Center, Tokyo, Japan ; Okuma, Y. ; Fuketa, H. ; Yasufuku, T.
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Scaling power supply voltages (VDD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower VDD, adaptive VDD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive VDD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International

Date of Conference:

19-23 Feb. 2012