We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Pyoungwon Park ; KAIST, Daejeon, South Korea ; Jaejin Park ; Hojin Park ; SeongHwan Cho

Injection locking is an effective method to reduce the jitter of clock generators especially for a ring oscillator-based PLL that has poor phase noise. While the use of injection locking reduces the output jitter, one disadvantage is that the output frequency can be changed only by integer multiples of the reference frequency, if it can be changed at all. In this work, an ADPLL-based clock generator is presented that employs a fractional-injection-locking method that exploits the multiphase output of a ring oscillator. The clock generator achieves an average of 4.23 psrms jitter and a frequency resolution of 1MHz while using a reference clock of 32MHz.

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International

Date of Conference:

19-23 Feb. 2012