A 28Gb/s source-series terminated TX in 32nm CMOS SOI

Upcoming standards such as OIF CEI-25LR and CEI-28SR demand transmitter circuits above 20Gb/s [1]-[3] with stringent jitter requirements. The SST driver topology, which has been previously demonstrated at lower data rates [4], is an attractive solution as it enables multiple termination options and low power consumption. In addition, its single-ended topology facilitates an architecture in which the delay mismatch between true and complementary output can be adjusted, as is desirable for data transmission over long cables. In this contribution, the architecture and design of the key components of a half-rate 28Gb/s SST TX are presented.