By Topic

A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

19 Author(s)

A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches . This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2.

Published in:

2012 IEEE International Solid-State Circuits Conference

Date of Conference:

19-23 Feb. 2012