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A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications

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9 Author(s)
Jong-Phil Hong ; Samsung Electron., Yongin, South Korea ; Sung-Jin Kim ; Jenlung Liu ; Nan Xing
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As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been sever- al approaches to convert analog systems to their digital counterparts and a high- resolution time-to-digital converter (TDC) is a key element for the digitalization of analog circuits. Recently TDCs using a noise shaping technique with oversampling have been introduced to improve resolution. However, they tend to be power hungry or require analog-intensive circuitry as they convert signals from the time domain to the voltage domain in order to perform arithmetic operations. A digital PLL (DPLL) is another crucial SoC component, and low-power area-efficient DPLLs are challenging to design. This paper presents a time-domain low-power ΔΣ TDC with a time-difference accumulator and an area-efficient, low-power, and fast-lock DPLL composed of a synthesizable bang-bang phase and frequency detector (BB-PFD), with a gain boosting mode and a pseudo-random number generator (PRNG).

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International

Date of Conference:

19-23 Feb. 2012