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3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth . A processor stacked with cache memory is one potential application of 3DI . This work describes the design and operation of a prototype of a 3D system, constructed by stacking a memory layer, built with eDRAM  and logic blocks from the IBM Power7™ processor L3 cache, and a “processor proxy” layer in 45nm CMOS technology  enhanced to include through-silicon vias (TSVs) . Unlike the previously reported 3D eDRAM , the 3D stack described here is constructed using 50μm pitch μC4's joining the front side of one thick chip to TSV connections on the back side of a thinned chip. TSVs are formed of Cu-filled vias that are ~20μm in diameter and <;100μm deep .