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Diverse spread spectrum clocking (SSC) generation requirements necessitate multiple reference clocks, extra pins, and off-chip components. With analog integer-n PLL-based clock generators, it is difficult to meet all these needs with a common reference clock. One disadvantage is that the frequency resolution in an integer-n PLL is limited by the reference frequency. A lower reference frequency limits the bandwidth and lock time, amplifies jitter from the reference, and increases the loop filter area. Additionally, analog PLLs suffer from unpredictable loop dynamics and clock skews with PVT, mismatch, and transistor leakage, further exacerbated by process scaling. Turning off and waking up an analog PLL requires charging or discharging loop filter capacitors which is inherently slow. This paper presents an all-digital clock generation architecture which (1) provides fractional-n capability in the digital domain; (2) implements SSC within the PLL loop; (3) performs digital clock deskew; and (4) provides dynamic loop bandwidth adjustment to shorten lock time.
Date of Conference: 19-23 Feb. 2012