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The T4 microprocessor introduces the next generation dual-issue, out-of-order SPARC core that delivers up to 5x integer and 7x floating-point single-thread performance improvement for both commercial and industry standard work- loads. Eight SPARC cores, a crossbar and a unified 16-way 4MB L3 cache are implemented in the same system-on-chip platform as the predecessor T3 to utilize established coherency (CLC), DDR3 (MCU), PCIE Gen2 (PEU) and 1G/10G Ethernet interfaces (NIL)). Further, T4's pin, thermal and power compatibility with the previous generation enables faster time to market for new multi-socket systems. The 403mm2 die has 855 million transistors of four different types and 12 metal layers fabricated using TSMC's 40nm process.
Date of Conference: 19-23 Feb. 2012