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The process variation among 512 DRAM samples is more than 30%. The performance variation of general circuits is predicted to be over 60% in 2012. In general, a single-die-based DRAM has a large process variation from chip to chip, which among other parameters, causes tAC (address access time) variation in the application system. In order to reduce the tAC variation, most highspeed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption. For TSV-based stacked dies, large tAC variantion results in higher power consumption due to short circuit current from data conflicts among shared I/Os. Since the number of I/Os for TSV-based stacked DRAM (TSV DRAM) might be 512 or more, the additional power consumption can be very high. Even though it is desirable in mobile DRAM to exclude the DLL because of the power cost, TSV DRAM for high-speed operation partially adopts a DLL in the master die. Our DLL-based data self-aligner (DBDA) reduces the data conflict time among stacked dies, consuming 283.2μW during read operation at 800Mb/s/pin. It dissipates 4.98μW in self-refresh mode with the help of leakage-current-reduction controller.