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Additional check node to improve the performance of LDPC codes in the error floor region

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3 Author(s)
Deka, K. ; Indian Inst. of Technol. Guwahati, Guwahati, India ; Rajesh, A. ; Bora, P.K.

This paper presents a new scheme to reduce the detrimental effect of the trapping sets in the regular and irregular low density parity check (LDPC) codes. By adding only one new check node and properly selecting its edges, the performance in the error floor region can be improved. Simulation results show that the proposed scheme decreases the bit error rate (BER) and frame error rate (FER) significantly in the high signal-to-noise ratio (SNR) region at the expense of negligible rate loss.

Published in:

Communications (NCC), 2012 National Conference on

Date of Conference:

3-5 Feb. 2012