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DC Offset Error Compensation for Synchronous Reference Frame PLL in Single-Phase Grid-Connected Converters

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4 Author(s)
Seon-Hwan Hwang ; Dept. of Electr. Eng., Kyungnam Univ., Changwon, South Korea ; Liming Liu ; Hui Li ; Jang-Mok Kim

This letter proposes a dc offset error compensation algorithm for synchronous reference frame phase-locked loop (PLL) in single-phase grid-connected converters. The errors generated from the grid voltage measurement circuits can be divided into dc offset and scaling errors. These errors may cause the undesirable periodic ripples with grid frequency in the synchronous reference frame PLL. As a result, the performance of the power conversion systems is degraded. In this letter, the effects of the dc offset and scaling errors are comprehensively analyzed based on the synchronous dq frame PLL. In particular, the dc offset error can be estimated and compensated by controlling the synchronous d-axis voltage in a PLL system to be zero. The proposed algorithm does not require any additional hardware and can be implemented by a simple proportional-integral controller and an integral operation. Experimental results are presented to demonstrate the effective- ness of the proposed dc offset error compensation algorithm.

Published in:

Power Electronics, IEEE Transactions on  (Volume:27 ,  Issue: 8 )

Date of Publication:

Aug. 2012

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