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Power Variability in Contemporary DRAMs

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3 Author(s)
Gottscho, M. ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; Kagalwalla, A.A. ; Gupta, P.

Technology scaling has led to significant variability in chip performance and power consumption. In this work, we measured and analyzed the power variability in dynamic random access memories (DRAMs). We tested 22 double date rate third generation (DDR3) dual inline memory modules (DIMMs), and found that power usage in DRAMs depends on both operation type (write, read, and idle) as well as data, with write operations consuming more than reads, and 1s in the data generally costing more power than 0s. Temperature had little effect (1-3%) across the C to 50 C range. Variations were up to 12.29% and 16.40% for idle power within a single model and for different models from the same vendor, respectively. In the scope of all tested 1 gigabyte (GB) modules, deviations were up to 21.84% in write power. Our ongoing work addresses memory management methods to leverage such power variations.

Published in:

Embedded Systems Letters, IEEE  (Volume:4 ,  Issue: 2 )