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Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD

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3 Author(s)
Te-Wen Liao ; Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Jun-Ren Su ; Chung-Chih Hung

This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-μm CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 3 )