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Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71-76 GHz and upper 81-86 GHz bands were designed and fabricated in 0.13%m SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve 60dB gain, 8.5 dB noise figure, -30 dBm IIP3, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency multiplier by four (quadrupler). It achieves output power P1dB of 0 to 11 dBm, Psat of 3.3 to 14 dBm, and consumes 850 mW.