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An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 µm CMOS process

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4 Author(s)
Yu-Hsuan Lin ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Jeng-Han Tsai ; Yen-Hung Kuo ; Tian-Wei Huang

A 24 GHz 29.8 mW Phase-lock-loop using 0.18 μm CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm2 without off-chip loop filter.

Published in:

Microwave Conference Proceedings (APMC), 2011 Asia-Pacific

Date of Conference:

5-8 Dec. 2011