By Topic

A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Andreas Axholt ; Dept. of electrical- and information technology, Lund University, 22100, Sweden ; Henrik Sjöland

This paper presents a fully integrated 60 GHz front-end for phased array receivers. For the first time in the literature a phase controlled phased locked loop (PC-PLL) is used for beamforming at 60 GHz. The front-end performs a two stage frequency down-conversion, first from 60 GHz to 20 GHz, then from 20 GHz to quadrature baseband. Both the local oscillator signals at 20 GHz and 40 GHz are generated by a single 20 GHz QVCO without any frequency multipliers. The measured results show an input return loss better than -10 dB between 57.5 GHz and 60.8 GHz, 15 dB voltage gain, and 9 dB noise figure. Two-tone measurements show a -12.5 dBm IIP3, 29 dBm IIP2, and -24 dBm ICP1dB. The phase control of the PLL has a resolution of 3.2 degrees and the control range exceeds 360 degrees. The chip consumes 80 mA from a 1.2 V supply, and measures 1400 μm × 660 μm (900 μm × 500 μm excl. pads) incl. LNA, mixers, and PC-PLL in a 90 nm RF CMOS process.

Published in:

Asia-Pacific Microwave Conference 2011

Date of Conference:

5-8 Dec. 2011