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A 60 GHz CMOS PLL synthesizer using a wideband injection-locked frequency divider with fast calibration technique

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4 Author(s)
Shima, T. ; Tokyo R&D Center, Panasonic Corp., Yokohama, Japan ; Sato, J. ; Mizuno, K. ; Takinami, K.

A 60 GHz phase-locked loop (PLL) using an inductor-less divide-by-3 injection locked frequency divider is presented. The PLL employs a simple and fast calibration algorithm which adjusts the locking range of the injection locked divider by measuring its free running frequency. The PLL is fabricated in 90 nm CMOS. The measured result shows the calibration algorithm converges within 15 μsec with only 6 iterations at all 4-channels defined by IEEE802.11ad draft standard using unlicensed 60 GHz bands, verifying the validity of the proposed approach.

Published in:

Microwave Conference Proceedings (APMC), 2011 Asia-Pacific

Date of Conference:

5-8 Dec. 2011

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