Area-time performance of VLSI FIR filter architectures based on residue arithmetic

The area-time (A/spl middot/T) optimization of a particular class of residue number system (RNS)-based FIR processors is discussed in this paper. To facilitate the optimization procedure, a number of performance models are introduced. Furthermore, moduli bases are attained that lead to RNS FIR filter architectures of minimal A/spl middot/T/sup 2/ product. The A/spl middot/T/sup 2/ performance models include the binary-to-residue and residue-to-binary conversion complexity. In particular, efficient Chinese remainder theorem (CRT) architectures are derived, based on multiply-by-constant units (MCUs), which are systematically designed by an introduced methodology. The A/spl middot/T/sup 2/ performance of the derived residue FIR filter architectures is found to surpass equivalent binary structures under certain conditions.