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Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces

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3 Author(s)
Pavlov, A. ; Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France ; Bechennec, J.-L. ; Etiemble, D.

We present a methodology to evaluate performance of the memory hierarchy of PC microcomputers. This methodology is based on synthetic bus traces which allow simulation of the memory hierarchy without having to build a model of the microprocessor. As a result, the simulation is orders of magnitude faster than an instruction level one but the methodology is not valid with a dynamically scheduled superscalar microprocessor.

Published in:

EUROMICRO 97. New Frontiers of Information Technology., Proceedings of the 23rd EUROMICRO Conference

Date of Conference:

1-4 Sept. 1997