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We present a simple technique for efficient cycle precise core based system simulator implementation. We first examine the current communication mechanisms in state-of-the-art digital embedded systems, and notice that few signals depend on signals set during the same cycle. Using a system model based on communicating finite state machines, we build a directed graph whose vertices are the FSMs, and whose arcs are the combinational, also known as Mealy, signals connecting them. We show that it is possible to schedule the order of evaluation of each FSM at compile-time as long as there is no cycle in this graph. We also show that using a topological sort on the graph provides a correct schedule. A system modeled in C including a MIPS R3000 microprocessor core, memories and a few other components interconnected on a PI-Bus simulated using this technique runs at around 150 K cycles per second on a Pentium 120.
Date of Conference: 1-4 Sept. 1997