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Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering

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4 Author(s)
Longxing Shi ; Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China ; Wei Zhao ; Jianhui Wu ; Chao Chen

A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 4 )