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The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator

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5 Author(s)
Jian Chen ; iPack Vinn Excellence Center, ICT School, KTH (Royal Institute of Technology), Kista, Stockholm, Sweden ; Liang Rong ; Fredrik Jonsson ; Geng Yang
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An improved architecture of polar transmitter (TX) is presented. The proposed architecture is digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma ΔΣ modulator for envelop modulation, and a H-bridge class-D power amplifier (PA) for differential signaling. The ΔΣ modulator is clocked using the phase modulated RF carrier to ensure phase synchronization between the amplitude and phase path, and to guarantee the PA is switching at zero crossings of the output current. An on-chip pre-filter is used to reduce the parasitic capacitance from packages at the switch stage output. The high over sampling ratio of the ΔΣ modulator move quantization noise far away from the carrier frequency, ensuring good in-band performance and relax filter requirements. The on-chip filter also acts as impedance matching and differential to single-ended conversion. The measured digital transmitter consumes 58 mW from a 1-V supply at 6.8 dBm output power.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:47 ,  Issue: 5 )
IEEE RFIC Virtual Journal
IEEE RFID Virtual Journal