Skip to Main Content
Higher operation temperatures and the current density increase of new IGBT generations make it more and more complicated to meet the quality requirements for power electronic modules. Especially the increasing heat dissipation inside the silicon leads to maximum operation temperatures of nearly 200 deg C. As a result new packaging technologies are needed to face the demands of power modules in the future. In case of the chip-to-substrate interconnect basically two technology trends for an improved die attach procedure became visible. On the one hand diffusion bonding has been presented, where the joint is formed from high melting intermetallics. On the other hand the chip-to-substrate interconnect can be realized by sintering silver particles, resulting in a monometallic porous die attach layer. This paper presents a comparison of these two technology trends with respect to their applicability for power electronics packaging.