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Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach

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5 Author(s)
Yoon-Deuk Seo ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Dongkyun Nam ; Byoung-Jin Yoon ; Il-Hyun Choi
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This paper presents a new low-power on-chip voltage reference less sensitive to the process variation in an 0.5 μm DRAM process where neither reliable BJT nor depletion MOS are available. The proposed voltage reference uses the MOS threshold voltage and a PTAT (proportional to the absolute temperature) voltage generated only from MOS transistors, and achieves considerably good performance at the total current of less than 8 μA with an external power supply voltage ranging from 2.8 to 4 V. The measured temperature coefficient is about 360 ppm/°C at temperatures ranging from 0°C to 100°C. In addition, an optimization technique is proposed to find a set of optimal parameters in designing circuits

Published in:

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Date of Conference:

7-10 Sep 1997