Referenced Items are not available for this document.
In this paper, a heuristic algorithm for free BDD node minimization is presented. This algorithm is designed to minimize small size FBDDs with application to synthesize pass transistor logic gate families. Experimental results based on 169 single output functions from MCNC benchmark two-level logic examples indicate 22 to 24% reduction of node count compared with initial ROBDD. Also, experimental results based on HWB functions (N=3-16) indicate node count reduced to 30 to 40% larger than the theoretical limit
Published in:
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Date of Conference: 7-10 Sep 1997
- Page(s):
- 201 - 205
- Meeting Date :
- 07 Sep 1997-10 Sep 1997
- ISSN :
- 1063-0988
- Print ISBN:
- 0-7803-4283-6
- INSPEC Accession Number:
- 5766810
- Conference Location :
- Portland, OR
- Digital Object Identifier :
- 10.1109/ASIC.1997.617005
- Product Type:
- Conference Publications
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