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Design and Performance Analysis of a 866-MHz Low-Power Optimized CMOS LNA for UHF RFID

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2 Author(s)
Li, J. ; Center for Res. in Analog & VLSI Microsyst. dEsign (CRAVE), Massey Univ., Albany, New Zealand ; Hasan, S.M.R.

An optimized 866 MHz CMOS LNA for UHF radio-frequency identification reader is presented. It achieves simultaneous impedance and minimum Fmin noise matching at a very low-power drain of 850 μW from a 0.7-V supply voltage. Compared to other GHz LNA designs, this UHF LNA design using sub-1 V supply voltage is quite challenging due to the inductor size and bias drain-related noise factor degradation. The LNA was fabricated using the 130-nm IBM CMOS process. Compared to previously reported narrow-band LNA designs, inclusion of the finite gds effect is found to improve the nanometric design optimization. The low-cost packaged LNA was tested using external lumped element and microstrip line matching. The LNA delivered a power gain (S21) of ≈17 dB and an input power reflection (S11 @ 866 MHz) of ≈ -30 dB. It had a minimum pass-band noise figure of around 2.2 dB and a third-order input-referred intercept point of ≈ -11.5 dBm.

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Industrial Electronics, IEEE Transactions on  (Volume:60 ,  Issue: 5 )