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Integrating a large number of embedded memories in System-on-Chips (SoC's) occupies up to more than 70% of the die size, thus requiring Built-In Self-Test (BIST) with the smallest possible area overhead. This paper analyzes MATS++(6N), March C-(10N), March SR(14N), and March CL(12N) test algorithms and shows that they cannot detect either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults (DRDFs) or both. Therefore to improve fault detection, an automation program is developed based on sequence operation (SQ) generation rules. However after solving the undetected fault, the outcome in term of its detection result of Static Double Cell Faults using the specified test algorithm especially Transition Coupling Faults (CFtrs), Write Destructive Coupling Faults (CFwds), Read Destructive Coupling Faults (CFrds) and Deceptive Read Destructive Faults (CFdrds) are observed.