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Design and Analysis of a Mesh-based Wireless Network-on-Chip

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3 Author(s)
Wen-Hsiang Hu ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, CA, USA ; Chifeng Wang ; Bagherzadeh, N.

Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture.

Published in:

Parallel, Distributed and Network-Based Processing (PDP), 2012 20th Euromicro International Conference on

Date of Conference:

15-17 Feb. 2012