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We present a single event transient (SET) propagation model that can be used to quantify the propagation likelihood of a given noise waveform trough CMOS logic gates. This analysis is key to predict if an SET induced within a combinational block is capable of causing an SEU. The model predicts the output noise characteristics given the input noise waveform for each gate, and can be applied to any CMOS technology through a one-time library parameter extraction process. Pulse propagation is described through continuous analytical functions that convert an SET pulse height and width at the gate input to an SET pulse height and width at its output. The noise transfer curves have relatively simple analytical continuous expressions suitable for an easy adoption within CAD tools, thus allowing the investigation of pulse propagation through an entire logic block. Comparison between simulations and model show a very good agreement for a commercial 65 nm technology.