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In this study, the authors present an optimisation method based on analytical resistance, inductance and capacitance (RLC) models for simultaneous reduction of both functional crosstalk noise and power supply noise caused by on-chip buses. This is achieved by intentional skewing of the relative timing of adjacent wires. The method is applicable to any number of bus wires and it takes into account both capacitive and inductive coupling between wires. The authors model the effect of skewing on both functional crosstalk in a distributed RLC bus and the power noise in the surrounding RLC power distribution network. The model is verified by comparing it with HSPICE in 65 nm technology, with the average error being 1.4%. The capability of the method in reducing problematic long-range inductive crosstalk noise is demonstrated in a case study where the maximum crosstalk noise is reduced from 0.20 to 0.05 V. Implementation and the use of the method in combination with other crosstalk reduction methods and power supply noise reduction methods are presented. The influence of the number of different skewing times is analysed.