As device geometries shrink to nanometers, increasing leakage current coupled with particle induced soft errors is exasperating the circuit reliability issues. In this paper, we first establish that independent solutions to these two problems can not lead to a good final solution. A more thoughtful and integrated design methodology is required to reconcile these two challenging issues. Next, we investigate the dependency of soft error rate on the body bias based leakage reduction method and introduce a novel body bias-dependent soft error model. We propose an optimization based and a heuristic driven approach to reduce leakage while satisfying the soft error rate limit. Our methods provide appropriate body bias configurations that lead to near-optimal total mean time to failure improvement of a circuit.
Published in:
VLSI Design (VLSID), 2012 25th International Conference on
Date of Conference: 7-11 Jan. 2012