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Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design

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2 Author(s)
Susmita Sur-Kolay ; Indian Stat. Inst., India ; Swarup Bhunia

Gigascale integration in recent semiconductor technology mandates design reuse in order to meet the design specifications in time. Electronic description of VLSI design being an intellectual property (IP), may be infringed upon during design reuse. This calls for incorporating techniques for intellectual property protection in the VLSI design flow. The IP of VLSI design, which culminates in fabrication of the integrated circuit, differs from other sources of IPs because in addition to its physical and structural description, it has also a behavioral specification which should remain unaltered after application of IP protection techniques. Security in activation of chips, especially in embedded systems, is an equally grave issue and has led to the paradigm of design-for-security. This tutorial aims at presenting the major concerns related to IP security that are significant to both the circuit designers and developers of CAD tools. The nature of threats are broadly categorized as (i) misappropriation by hacking during electronic commerce and intentional reselling mostly at design level, and (ii) unauthorized design retrieval. Various attack models and the mechanisms for effective counter measures such as encryption, obfuscation, watermarking and fingerprinting, and certain analytic methods derived from the behavioral aspect, specific to chip designs, will be discussed. First, the scenario of digital rights management, attack models and security goals will be described. Next, the existing approaches for protection of soft IPs such as HDL codes, firm IPs especially at the value-added layout level, and hard IPs including DFM-enhanced layout will be presented. This will include a number of published research results by the presenters. Finally, the recent advances in tackling security issues for design of smart cards and crypto processors will be surveyed.

Published in:

2012 25th International Conference on VLSI Design

Date of Conference:

7-11 Jan. 2012