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Robust decoder architecture for multi-level flash memory storage channels

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2 Author(s)

Multi-level-cell (MLC) flash memory comprises of cells which can be programmed to multiple levels. Recent MLC flash memory systems support 3 bits per cell to 4 bits per cell which means that the individual cells are programmed to 8 or 16 distinct levels respectively. MLC flash has higher raw bit error rate (rber) than the single bit per cell flash. This calls for the use of sophisticated error control coding (ECC) schemes like LDPC codes. The flash memory channel is usually modeled with level distributions having Gaussian probability density function. However, the Gaussian distribution is not a good fit for practical NAND channels. Even for the beginning of life of the flash memory device, this model has to be replaced by a more realistic model. With erases and re-writes, the channel towards the end of life of the device is far from Gaussian and floating-gate to floating-gate coupling and charge loss not only increases the raw bit error rate but causes the level distributions to become asymmetric. Given such channel impairments, if the LDPC decoder assumes Gaussian level distributions, its performance can degrade considerably. Hence, modifications are required in the decoding algorithm to cope up with the channel distortions. In order to keep the hardware costs within limits, simple schemes with minimal hardware increase are desirable to keep up the performance. In this paper, the flash channel degradations are first enlisted and then simple solutions are proposed which keep the performance in check as the flash memory transits from a channel with moderate impairments to the end of life condition, where the level distributions for the different levels are highly asymmetric.

Published in:

Computing, Networking and Communications (ICNC), 2012 International Conference on

Date of Conference:

Jan. 30 2012-Feb. 2 2012