Optimization of f/sub T/, BVCEO and /spl beta/ with selectively implanted collectors in BiCMOS technology

This paper shows that by implanting the collector of its NPN transistors with N-type impurities and by choosing the right combination of the dopants, dose and energy, f/sub T/ can be improved significantly in a BiCMOS process. The improvement is mask selectable, i.e., it allows two sets of transistors: (1) SIC, "Selectively Implanted Collector" transistors and (2) the original process NPNs which are unchanged, to be created side by side. Simulations done by incorporating the SIC implant on the experimentally verified numerical model simulations of the original process showed that f/sub Tmax/ can be improved from 13.5 GHz to 21 GHz in a 0.6-0.8 /spl mu/m BiCMOS process. It is also shown that the SIC implanted transistors, when optimum dose and energy values are used, will yield transistors whose /spl beta/ will not differ more than 30% from the /spl beta/ the mainstream BiCMOS process yields.