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Ultra low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers

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4 Author(s)
Nomura, K. ; Advanced LSI Technology Laboratory Corporate Research and Development Center, Toshiba Corporation, 1, Komukai-Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan ; Abe, K. ; Yoda, H. ; Fujita, Shinobu

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.3677444 

This paper presents novel processor architecture for HP-processor with MRAM/SRAM-based hybrid cache memory. By simulations of HP-processor using MTJs, it has been clarified that total power of the HP-processor using perpendicular-(p-)STT-MRAM [H. Yoda, etal, Current Appl. Phys. 10, e87 (2010)] can be reduced by 50.2% without any degradation of operation speed. This is the first report on effectively decreasing total power of HP-processors with no degradation of performance using magnetic memory. The presented architecture will be the first step to realize the next generation “normally-off computers.”

Published in:

Journal of Applied Physics  (Volume:111 ,  Issue: 7 )

Date of Publication:

Apr 2012

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