A novel gate assist circuit for quick and stable driving of SiC-JFETs in a 3-phase inverter

A novel gate drive circuit for an SiC-JFET in a bridge circuit that ensures a quick and stable switching has been proposed and demonstrated. The gate voltage of an off-state transistor tends to rise up due to a steep drain-source voltage change caused by turning-on of the transistor in the other side of the bridge circuit. Even though the gate terminal is kept in the off-state by a voltage source, the abovementioned steep voltage change induces a non-off-state voltage across the parasitic inductance in the gate wiring. As a result, the capability of an SiC transistor for high switching speed in a bridge circuit is limited. The novel gate assist circuit using a PNP transistor with additional capacitors can overcome this limit. It was verified experimentally that the new gate assist circuit improves the turn-on delay time by approximately six fold and the turn-off time by 72%.