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An efficient memory block selection strategy to improve the performance of cache memory subsystem

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1 Author(s)
Asaduzzaman, A. ; Dept. of Electr. Eng. & Comput. Sci., Wichita State Univ., Wichita, KS, USA

Although cache improves performance by reducing the speed-gap between the CPU and main memory, cache increases the timing unpredictability due to its dynamic nature. Cache also requires significant amount of power to be operated. Unpredictability and power consumption become even worse in multicore systems due the presence of multiple levels of caches. Recent studies indicate that predictability can be increased and total power consumption can be decreased without compromising performance by locking appropriate memory blocks. The success of cache locking depends on the accurate selection of blocks to be locked. In this work, we propose an easy but efficient memory block selection strategy to enhance cache locking and cache replacement enactment and overall cache memory subsystem performance. Proposed scheme determines the blocks that produce more cache misses if not locked and stores the block address and miss information (BAMI) at cache level. Cache locking technique should lock memory blocks with higher cache misses and cache replacement policy should select victim blocks with lower cache misses using BAMI. We simulate single-core and multi-core systems, both with two-level cache memory subsystem, to evaluate the proposed block selection scheme. Experimental results show that the predictability can be improved by increasing hit ratio up to 11% and total power consumption can be decreased up to 20% by using our memory block selection scheme.

Published in:

Computer and Information Technology (ICCIT), 2011 14th International Conference on

Date of Conference:

22-24 Dec. 2011