An implementation of a real-time and parallel processing ECG features extraction algorithm in a Field Programmable Gate Array (FPGA)

The objective of the paper is to report a development of real-time and parallel processing algorithm to implement it into a Field Programmable Gate Array (FPGA) for the electrocardiogram (ECG) signals feature extraction. The prototyped system will be extracting the ECG features and tested as a System on Chip (Soc) design. The performance of algorithm was tested against MATLAB routine and validated results based on the MIT-BIH Arrhythmia database which has been annotated by cardiologists. The ECG signals from five volunteers were acquired, tested, analyzed and displayed in on line. This overall detection tolerance of the algorithm was 0.01 seconds.