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Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can provide substantial coding gain with polynomial complexity. To reduce the complexity of ASD decoders, reencoding and coordinate transformation need to be applied, which require a reencoder and an erasure decoder. In the reencoded and transformed ASD decoders, these two blocks take a significant part of the overall decoder area and may limit the achievable throughput. In this brief, the reencoder design based on direct polynomial multiplication is further simplified by reformulating the involved equations. Moreover, two innovative area-reducing methods are proposed for the transformed coordinate computation. Efficient architectures are developed for the proposed schemes, and two reencoders are implemented using 0.18- CMOS technology. For a (255, 239) RS code, both reencoders can achieve throughput of at least 1.77 Gb/s and more than 30% higher efficiency in terms of throughput-over-area ratio than prior work. With minor modifications, the proposed design can also be employed to implement efficient erasure decoding.