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A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz {\rm f}_{\rm T} BiCMOS Process

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15 Author(s)
Van de Sande, F. ; Agilent Technol., Rotselaar, Belgium ; Lugil, N. ; Demarsin, F. ; Hendrix, Z.
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We present a complete signal generator with integrated digital-to-analog convertor (DAC) on a chip which can generate complex waveforms at up to 7.2 GSa/s with 14 bit resolution or at up to 12 GSa/s with 12 bit resolution. The 3 dB bandwidth is 4.4 GHz. The chip includes digital signal processing (DSP) logic for agile generation of wideband modulated RF signals (up to 480 MHz modulation bandwidth) as well as high fidelity chirp and continuous wave signals. There is also DSP for integral non-linearity error reduction and suppression of clock sub-harmonics. The DAC uses a segmented architecture with 4 unary most significant bits and an R/2R ladder for the 10 binary least significant bits. Distributed resampling is applied to all current sources to improve the dynamic performance. At 7.2 GSa/s it delivers at least 67 dB spurious free dynamic range (SFDR) across the whole Nyquist region and an SNR of 62 dB. It demonstrates - 157 dBc/Hz phase noise at 10 kHz offset from a 1 GHz carrier, 22 dB better than known synthesized signal generation instruments. The chip is built in a 165 GHz fT, 130 nm BiCMOS process and is packaged in a 780 ball BGA.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 4 )

Date of Publication:

April 2012

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