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This paper presents a D-PHY chip design for MIPI (Mobile Industry Processor Interface) standard. The MIPI is a flexible, source-synchronous serial interface standard connecting a host processor to a display and camera modules as used in mobile devices. The D-PHY consists of LP (low-power) mode block, HS (high-speed) mode block and control blocks. We implemented D-PHY chip using 0.13-um CMOS process under 1.2V supply. As a result, HS mode shows 1Gbps with jitter 5% and 0.74mW power consumption.