By Topic

Design of a D-PHY chip for mobile display interface supporting MIPI standard

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

This paper presents a D-PHY chip design for MIPI (Mobile Industry Processor Interface) standard. The MIPI is a flexible, source-synchronous serial interface standard connecting a host processor to a display and camera modules as used in mobile devices. The D-PHY consists of LP (low-power) mode block, HS (high-speed) mode block and control blocks. We implemented D-PHY chip using 0.13-um CMOS process under 1.2V supply. As a result, HS mode shows 1Gbps with jitter 5% and 0.74mW power consumption.

Published in:

Consumer Electronics (ICCE), 2012 IEEE International Conference on

Date of Conference:

13-16 Jan. 2012