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Neural CMOS-Integrated Circuit and Its Application to Data Classification

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4 Author(s)
Goknar, I.C. ; Dept. of Electron. & Commun. Eng., Dogus Univ., Istanbul, Turkey ; Yildiz, M. ; Minaei, S. ; Deniz, E.

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

Published in:

Neural Networks and Learning Systems, IEEE Transactions on  (Volume:23 ,  Issue: 5 )

Date of Publication:

May 2012

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