Effect of annealing ambient and temperature on the electrical characteristics of atomic layer deposition Al2O3/In0.53Ga0.47As metal-oxide-semiconductor capacitors and MOSFETs

In this work, we investigate the effect of forming gas annealing (FGA) on n-type and p-type In0.53Ga0.47As MOS capacitors with atomic layer deposition (ALD) Al2O3 high-κ dielectric. The as-deposited samples have a significant amount of fixed charge in the bulk of the gate dielectric and at the dielectric/semiconductor interface, which causes the flatband voltage (VFB) to have an oxide thickness dependent shift. Through FGA, we successfully (1) reduce the amount of bulk and interface fixed charge in the Al2O3, and (2) improve the Al2O3/InGaAs interface. The reduction in fixed charge is verified through an alignment of the VFB across all dielectric thicknesses. The gate stack improvement is qualitatively illustrated through a sharper capacitance-voltage (C-V) curve and quantitatively verified through a reduction of the interface trap density (DIT). The effect of the annealing temperature (300–400 °C) and ambient (N2 and forming gas (FG)) are investigated in detail through electrical characterization by C-V, I-V, DIT, fixed charge density (QF), and interface sheet charge (QIT) measurements. We find that there exists a trade-off where higher annealing temperatures result in a lower DIT, but comes at the cost of higher gate leakage. Furthermore, by comparing the effect of annealing in inert N2 versus FG, we are able to distinguish the effect of hydrogen in the FGA from the purely thermal effects of annealing. We discover that hydrogen passivation of dangling bonds and border traps is responsible for improving the interfacial properties, while the thermal budget is responsible for minimizing the fixed charge. Finally, we study the benefit of FGA on InGaAs nMOSFET device performance and demonstrate that the on-current increases by 25% after annealing at 350&#- 2009;°C for 30 min. A thorough understanding of the impact of FGA is crucial for threshold voltage tuning and improvement of the InGaAs MOSFET gate stack.